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數字集成電路面試常見問題

對集成電路輻射硬度的常見誤解 (Common misconceptions on the radiation hardness of integrated circuits)

Space exploration was always fascinating, and recent developments have reignited the interest to the heights never seen since the last man stood on the Moon. People argue about Mars exploration and features of spaceships as their grandparents would』ve done if the internet existed fifty years ago. I’m an electronics engineer working in the aerospace industry, so I know a thing or two about the technical background of this stuff — and I see that these things aren’t common knowledge, and people often have significantly skewed ideas about the reasons behind some devices and decisions. Namely, I』d love to speak about some misconceptions related to radiation hardened integrated circuits and the means of their protection against radiation-induced damage. But, I warn you, this text will be relatively long.

太空探索總是令人著迷，最近的發展使人們對自最後一個人站在月球上以來從未見過的高度重新產生了興趣。 人們爭論著火星的探索和宇宙飛船的特徵，就像網際網路在五十年前存在時他們的祖父母所做的那樣。 我是航空航天業的電子工程師，所以我對這些技術的背景知識了解一兩件事，而且我發現這些知識不是常識，人們通常對背後的原因有明顯的偏見一些設備和決定。 即，我很想談談與輻射硬化集成電路有關的一些誤解，以及防止輻射引起的損害的保護手段。 但是，我警告您，這段文字會比較長。

我為什麼要寫這個？ (Why do I write this?)

The most popular theses about radiation hardness of ICs are the following:

關於IC輻射硬度的最受歡迎的論文如下：

1. Radiation hardened chips are not needed at all. CubeSats are just fine with chips from the nearest store, very ordinary Lenovo laptops work on the ISS without any problems, and even NASA-commissioned Orion onboard computer is based on a commercial microprocessor!

   根本不需要經過輻射硬化的晶片。 CubeSats可以與附近商店的晶片配合使用，非常普通的Lenovo筆記本電腦可以在ISS上正常工作，甚至NASA委託的Orion車載計算機都基於商用微處理器！

2. Satellites don’t need computational power, but they need these magical radiation hardened chips, so most of them use very old but extremely robust designs from the eighties, like TTL quad NAND gates.

   衛星不需要計算能力，但是它們需要這些神奇的輻射硬化晶片，因此大多數衛星都使用80年代的非常古老但極其堅固的設計，例如TTL四與非門。

3. A thesis that complements the previous one: it is impossible to achieve radiation hardness on modern process nodes. Ionizing particles just tear small transistors apart. So, the use of these TTL NAND gates is not just justified, it’s the only way to go.

   這是對前一個論文的補充：在現代Craft.io節點上不可能達到輻射硬度。 電離粒子只會將小的電晶體撕開。 因此，使用這些TTL NAND門並不合理，這是唯一的方法。

4. It’s necessary and sufficient to use silicon on insulator (SOI) or silicon on sapphire (SOS) technology to achieve radiation hardness.

   必須使用絕緣體上矽(SOI)或藍寶石上矽(SOS)技術來達到輻射硬度。

5. All military-grade chips are radiation hardened and all radiation hardened chips are military-grade. If you have a military-grade IC, you can safely launch it into outer space.

   所有軍用級晶片都經過輻射硬化，所有防輻射晶片都經過了軍工級認證。 如果您擁有軍用級IC，則可以安全地將其發射到太空中。

As one can see, these theses directly contradict each other — which makes arguing on the internet even funnier, especially if you take into account that not a single one of them is true.

可以看到，這些論點直接相互矛盾，這使在網際網路上爭論變得更加有趣，尤其是如果考慮到其中沒有一個是真的。

Let’s start with an important disclaimer: radiation hardness is not the Holy Grail of integrated design for space and other similar environments. It’s just a bunch of checkboxes in the long requirements list, which typically includes reliability, longevity, wide temperature range, tolerance to electrostatic discharge, vibrations and many more. Everything that can compromise reliable functioning through the entire lifetime is important, and most applications requiring radiation tolerance also assume the impossibility of repair or replacement. On the other hand, if something is wrong with one of the parameters, system-level designers of the final can often find a workaround — tighten temperature requirements, use cold spares or additional protection circuitry — whatever is suitable. The same approach can be fine when dealing with radiation effects: majority voting, supply current control and reset are very common means that are often effective. But it's also often when a brand new radiation hardened IC is the only good way to meet mission requirements.

讓我們從一個重要的免責聲明開始：輻射硬度不是用於太空和其他類似環境的集成設計的聖杯。 在很長的要求列表中，它只是一堆複選框，通常包括可靠性，壽命，寬溫度範圍，對靜電放電的耐受性，振動等等。 在整個生命周期內都會影響可靠功能的所有因素都很重要，並且大多數需要防輻射的應用也都認為不可能進行修理或更換。 另一方面，如果其中一個參數出了點問題，則最終的系統級設計人員通常可以找到解決方法-嚴格控制溫度，使用冷備件或附加保護電路-適用。 處理輻射效應時，可以使用相同的方法：多數表決，電源電流控制和重置是非常有效的非常普遍的方法。 但是，通常只有全新的輻射硬化IC是滿足任務要求的唯一好方法。

It is also useful to remember that the developers of special-purpose systems are the same people as any other developers. Just like anyone else, they normally write code filled with crutches to be ready for yesterday's deadline and want more powerful hardware to mask their sloppy job; some would』ve used Arduino if it was properly certified. And it’s also obvious that people who create requirements are rarely really concerned with any limitations and want to have the same as in commercial systems, but more reliable and radhard. Therefore, modern processes are more than welcome in radhard electronics — system designers would love to have large amounts of DRAM, multi-core processors, and the most advanced FPGAs. I have already mentioned that there could be workarounds for mediocre radiation tolerance, so the use of commercial chips is mostly limited by the lack of data on what problems are than by the problems themselves or by the commercial status of the chips.

記住，專用系統的開發人員與任何其他開發人員都是同一個人，這也很有用。 就像其他任何人一樣，他們通常會寫滿拐杖的代碼，以準備在昨天的截止日期前完成工作，並希望有更強大的硬體來掩蓋他們的草率工作。 如果經過適當的認證，有些人會使用Arduino。 同樣顯而易見的是，創建需求的人很少真正關心任何限制，並希望與商業系統中的局限性相同，但更可靠，更可靠。 因此，現代Craft.io在radhard電子產品中非常受歡迎-系統設計人員希望擁有大量DRAM，多核處理器和最先進的FPGA。 我已經提到過，對於中等的輻射耐受性可能存在變通辦法，因此商用晶片的使用主要受到缺乏關於什麼問題的數據的限制，而不是受到問題本身或晶片商業地位的限制。

什麼是輻射效應 (What are radiation effects)

The very concepts of "radiation hardness" and "radiation hardened IC" are enormous simplifications. There are many different sources of ionizing and non-ionizing radiation, and they affect the functioning of microelectronic devices in multiple ways. The tolerance to different sets of conditions and varying levels of exposure for different applications is not the same, so a 「radiation hardened」 circuit designed for low earth orbit is absolutely not obliged to work in a robot parsing debris in Chernobyl or Fukushima.

「輻射硬度」和「輻射硬化IC」這兩個概念非常簡化。 電離輻射和非電離輻射有許多不同的來源，它們以多種方式影響微電子設備的功能。 對於不同的條件，對於不同的條件集和不同的暴露水平，其容忍度是不一樣的，因此，絕對不需要在車諾比或福島的機器人中使用為低地球軌道設計的「輻射硬化」電路來解析碎片。

Ionizing radiation is called so because the deceleration of an incoming particle in a substance releases the energy and ionizes the substance. Each material has its own energy required for ionization and the creation of an electron-hole pair. For silicon it is 3.6 eV, for its oxide — 17 eV, for gallium arsenide — 4.8 eV. The energy release can also 「shift」 an atom out of the correct place in the crystal lattice (21 eV must be transferred to shift a silicon atom). Electron-hole pairs created in a substance can produce different effects in an integrated circuit. Therefore, radiation effects can be divided into the four large groups: the effects of total ionizing dose (TID), the dose rate effects, single event effects (SEE), and the non-ionizing effects called the displacement damage. This separation is somewhat arbitrary: for example, irradiation with a stream of heavy ions causes both single event effects and accumulation of a total ionizing dose.

之所以稱為電離輻射，是因為物質中傳入粒子的減速會釋放能量並使物質離子化。 每種材料都有其自身的能量，這些能量用於電離和創建電子-空穴對。 矽為3.6 eV，氧化物為17 eV，砷化鎵為4.8 eV。 能量釋放還可以使原子「移出」晶格中的正確位置(必須轉移21 eV才能移出矽原子)。 在物質中產生的電子-空穴對可以在集成電路中產生不同的效果。 因此，輻射效應可分為四大類：總電離劑量(TID)效應，劑量率效應，單事件效應(SEE)和稱為位移損傷的非電離效應。 這種分離在某種程度上是任意的：例如，重離子流的照射會導致單事件效應和總電離劑量的累積。

總電離劑量 (Total ionizing dose)

The total absorbed dose of radiation is measured in units called 「rad」, with an indication of the substance absorbing the radiation. 1 rad = 0.01 J/kg, it’s the amount of energy released in an elementary unit of weight in a given substance. Gray, which is a 100 rad (or 1 J/kg) is another, albeit, rarer unit. It is somewhat important to understand the same amount of ionizing particles released by a source of radiation (called radiation exposure) will be translated into different levels of absorbed dose in different substances. The material of choice for silicon ICs is silicon oxide. That’s because very low hole mobility in SiO2 causes charge accumulation in oxide producing various total dose effects. Typical dose levels for commercial circuits are in the range of 5-100 krad (SiO2). The levels that are in actual demand for some practical applications start around 30 krad (SiO2) and go as far as a few Grad (SiO2), depending on the purpose of the chip. Yes, Gigarads. The lethal dose for a human is around 6 Gray.

輻射的總吸收劑量以稱為「 rad」的單位進行測量，並指示吸收輻射的物質。 1 rad = 0.01 J / kg，它是指定物質中基本重量單位釋放的能量。 灰色是100弧度(或1焦耳/千克)，是另一個雖然較稀有的單位。 了解輻射源釋放的相同數量的電離顆粒(稱為輻射暴露)將轉化為不同物質中不同劑量的吸收劑量，這一點有點重要。 矽IC的選擇材料是氧化矽。 這是因為SiO2中非常低的空穴遷移率會導致氧化物中的電荷積累，從而產生各種總劑量效應。 商業電路的典型劑量水平在5-100 krad(SiO2)的範圍內。 在某些實際應用中，實際需要的電平大約為30 krad(SiO2)，最高可達幾個Grad(SiO2)，具體取決於晶片的用途。 是的，吉加拉德。 一個人的致死劑量約為6格雷。

The TID effects are mostly associated with the accumulation of positive charge in dielectrics. They manifest themselves in CMOS circuits in several main ways:

TID效應主要與電介質中正電荷的積累有關。 它們以幾種主要方式出現在CMOS電路中：

1. Threshold voltage shift. For n-channel transistors, the threshold is usually reduced (but the dependence may be non-monotonic, especially at high doses), while for p-channel transistors it increases. The shift magnitude correlates to gate oxide thickness and decreases with process node. In older technologies, n-MOSFET threshold shift can cause functional failure when n-channel transistors stop closing and p-channel ones stop opening. This effect is less important in submicron technologies, but it can still give a lot of headaches to analogue designers.

   閾值電壓漂移。 對於n溝道電晶體，閾值通常會降低(但相關性可能是非單調的，尤其是在高劑量時)，而對於p溝道電晶體，閾值會增加。 偏移量與柵極氧化物的厚度相關，並且隨Craft.io節點而減小。 在較舊的技術中，當n溝道電晶體停止關閉而p溝道電晶體停止打開時，n-MOSFET閾值偏移會導致功能故障。 在亞微米技術中，這種影響並不那麼重要，但是它仍然會使模擬設計人員感到頭疼。

2. Leakage currents flow through parasitic channels opened by an excessive charge in isolating oxides, either from source to drain of the same device, or from one transistor to another. In the first case, a parasitic transistor controlled by the total dose is formed in parallel to the main one. The severity of this effect is highly technology-dependent as the exact shape of isolated oxide matters. Therefore, there is no direct correlation to process nodes, and there is no good way to guess which commercial device will have better or worse TID hardness.

   漏電流流過由隔離氧化物中的過量電荷打開的寄生通道，這些寄生通道從同一器件的源極到漏極，或者從一個電晶體流向另一個電晶體。 在第一種情況下，由總劑量控制的寄生電晶體與主電晶體並聯形成。 這種影響的嚴重程度在很大程度上取決於技術，因為隔離氧化物的確切形狀至關重要。 因此，與Craft.io節點沒有直接關係，也沒有很好的方法來猜測哪個商業設備的TID硬度會更好或更差。

3. Charge carrier mobility decreases due to scattering on accumulated defects. The influence of this factor on submicron digital circuits on silicon is small, but it is a way more important for power transistors (including GaN HEMT).

   電荷載流子遷移率由於累積缺陷上的散射而降低。 這個因素對矽上的亞微米數字電路的影響很小，但是對於功率電晶體(包括GaN HEMT)而言，這是一種更為重要的方法。

4. 1/f noise increase caused by parasitic edge transistors. It is important for analogue and radio frequency circuits and becomes more important at lower process nodes when the influence of other TID effects gradually decreases.

   由寄生邊緣電晶體引起的1 / f噪聲增加。 這對於模擬和射頻電路很重要，並且在其他TID效應的影響逐漸減小時，在較低的過程節點處變得尤為重要。

A quick word on bipolars: the main TID effect there is gain decrease due to leakage-related base current increase. Another bipolar-specific effect is their (non-mandatory) rough reaction to the dose collection at low speed, so-called ELDRS (Enhanced Low Dose Rate Sensitivity). This effect complicates the testing and makes it more expensive. And the worst part is that many CMOS circuits contain a few bipolars (namely in voltage reference circuits) — and therefore can also be susceptible.

一個關於雙極的簡短說明：由於洩漏相關的基極電流增加，主要的TID效應會導致增益降低。 另一個雙極特異性效應是它們在低速下對劑量收集的(非強制性)粗略React，即所謂的ELDRS(增強的低劑量率敏感性)。 這種效果使測試複雜化並使其更加昂貴。 最糟糕的是，許多CMOS電路都包含一些雙極性(即在參考電壓電路中)，因此也容易受到影響。

劑量率效應 (Dose rate effects)

Another effect related to dose rate is when dose accumulation is so fast that such a large number of electron-hole pairs is generated that a huge excessive electric charge is overflowing every node in the chip and is causing a temporary loss of functionality and sometimes a latchup of parasitic thyristor between supply and ground. The non-functioning time is the usual measure of sensitivity to this kind of effect and it's normally seen in military standards like Mil-Std-883.

與劑量率有關的另一個影響是，劑量累積如此之快，以至於產生了如此大量的電子-空穴對，以至於晶片中的每個節點都溢出了巨大的過量電荷，並導致功能暫時性喪失，有時甚至閉鎖電源和地之間的寄生晶閘管的數量。 非工作時間是對這種影響的敏感度的通常度量，通常在軍事標準(如Mil-Std-883)中看到。

Total dose rate effects are the reason for 「silicon on sapphire」 (SOS) and 「silicon on insulator」 (SOI) technology creation and adoption: the best way to reduce the amount of charge inserted into active devices by the flow of ionizing particles is to cut their electrical connection to the enormously big substrate (and to each other). Why are these effects important? An extremely high dose rate for a short time is a typical consequence of a nuclear explosion, and military guys all around the world deeply care about this matter. Luckily for us, SOI proved to be advantageous in many other applications and therefore became widespread in normal life.

總劑量率效應是創建和採用「藍寶石上的矽」(SOS)和「絕緣體上的矽」(SOI)技術的原因：減少通過電離粒子流插入有源器件中的電荷量的最佳方法是切斷它們與非常大的基板(以及彼此之間)的電連接。 為什麼這些影響很重要？ 短時間內的極高劑量率是核爆炸的典型結果，世界各地的軍方對此事都深表關切。 對我們來說幸運的是，SOI在許多其他應用中被證明是有優勢的，因此在正常生活中變得越來越普遍。

單事件效果 (Single event effects)

Single event effects (SEE) are associated with a measurable effect from the strike of a single ionizing particle. They can be divided into two large groups:

單事件效應(SEE)與單個電離粒子撞擊的可測量效應相關。 它們可以分為兩大類：

1. Non-destructive events include bit flips or upsets (SEU) in a variety of storage elements (cache memory cells, register files, FPGA configuration memory, etc.) and transient voltage spikes (SET) in combinational logic and in analogue circuits. The main feature of these effects is that they do not lead to the physical destruction of the chip and can be corrected by software or hardware. Moreover, single event transients are self-corrected after some arbitrarily short time. Memory upsets are the most known of these effects as they constitute a lion's share of failures due to the enormous amount of memory in modern digital ICs.

   無損事件包括各種存儲元件(高速緩存存儲單元，寄存器文件，FPGA配置存儲器等)中的位翻轉或翻轉(SEU)，以及組合邏輯和模擬電路中的瞬態電壓尖峰(SET)。 這些影響的主要特徵是它們不會導致晶片的物理損壞，可以通過軟體或硬體進行糾正。 此外，單事件瞬變會在任意短時間後自動校正。 存儲器故障是這些影響中最著名的，因為現代數字IC中存在大量的存儲器，因此它們構成了故障的絕大部分。

2. Destructive events are Single-Event latchup (SEL) effect and a variety of fortunately rarer catastrophic failures like transistor burnout of gate rupture. Their distinctive feature is that they are, well, destructive and irreversibly damage the chip if occurred. The specific case of the latchup is distinctive as the very fast power off can often (but not always!) save the chip. Circuits for supply current monitoring and cycling are fairly popular as a latchup protection measure. Other destructive effects uncommon on CMOS circuitry, but are a serious threat for some types of flash memory and for high voltage devices, including power switches.

   破壞性事件包括單事件閂鎖(SEL)效應以及各種幸運的罕見災難性故障，例如電晶體對柵極破裂的燒壞。 它們的獨特之處在於，它們一旦發生就會具有破壞性且不可逆轉地損壞晶片。 閂鎖的特殊情況很獨特，因為非常快速的斷電通常可以(但不總是如此)節省晶片。 作為閉鎖保護措施，用於電源電流監視和循環的電路相當流行。 其他破壞性影響在CMOS電路上並不常見，但對某些類型的快閃記憶體和包括電源開關在內的高壓設備則構成嚴重威脅。

Figure 1. Experimental data on single event effects rate. Taken from J. Barth et al., "Single event effects on commercial SRAMs and power MOSFETs: final results of the CRUX flight experiment on APEX", NSREC Radiation Effects Data Workshop, 1998

圖1.單事件影響率的實驗數據。 摘自J. Barth等人，「對商用SRAM和功率MOSFET的單事件效應：在APEX上進行CRUX飛行實驗的最終結果」，NSREC輻射效應數據研討會，1998年

Looking at figure 1, one can see that the worst case is about one upset per two hundred days... per bit. Yes, every bit in memory is about to be affected twice per years. But when we have Megabits or Gigabytes of memory, it's always compromised, right? Yes, that's a problem, and there are techniques to address this problem, but more on that a bit later.

從圖1可以看出，最壞的情況是每200天……每位發生一次故障。 是的，內存中的每一位每年將受到兩次影響。 但是，當我們擁有兆位或千兆字節的內存時，它總是會受到損害，對吧？ 是的，這是一個問題，並且有一些技術可以解決此問題，但稍後會對此進行更多介紹。

The specific energy yield of an ionizing particle strike is called 「linear energy transfer」 (LET) and is measured (MeV * cm^2)/mg. LET non-linearly and non-monotonously depends on particle energy and is also related to the path length, which can vary from hundreds of nanometers to hundreds of millimeters for relevant particles and materials. Basically, most ionizing particles just punch through an IC and fly back to outer space. Low energy particles are much more common in a real space environment (see Figure 2). Important LET values are 30 (corresponding to ions of iron) and 60/80 (which are normally considered the highest LET values to be taken into account). Another important figure is 15 MeV * cm ^ 2/(mg) — the maximum LET of products of the nuclear reaction between a silicon atom and a proton or a neutron. Protons are important as they make up a significant part of solar radiation. Whilst they have very low LET on their own, the probability of the above mentioned nuclear reaction is high enough to create a lot of events, especially in van Allen belts or during solar bursts. Protons can also interact with nuclei of heavier elements, like tungsten (used in contacts) or tantalum (popular anti-TID shielding material). Such secondary effects are the second most important reason not to pack your space-bound chips into led covers in an attempt to increase their radiation hardness. The first one is, by the way, the launch price per kilo.

電離粒子撞擊的比能量產率稱為「線性能量轉移」(LET)，並以(MeV * cm ^ 2)/ mg進行測量。 LET非線性且非單調取決於粒子能量，並且還與路徑長度有關，對於相關的粒子和材料，路徑長度可能從數百納米到數百毫米不等。 基本上，大多數電離粒子只是穿過IC，然後飛回太空。 在現實空間環境中，低能粒子更為常見(請參見圖2)。 重要的LET值是30(對應於鐵離子)和60/80(通常被認為是要考慮的最高LET值)。 另一個重要的數字是15 MeV * cm ^ 2 /(mg)-矽原子與質子或中子之間的核React產物的最大LET。 質子很重要，因為它們構成了太陽輻射的重要組成部分。 儘管它們自己的LET很小，但上述核React的可能性很高，足以引發很多事件，尤其是在範艾倫帶或太陽爆發時。 質子還可以與重元素的原子核相互作用，例如鎢(用於接觸)或鉭(常用的抗TID屏蔽材料)。 這種次要效果是第二個最重要的原因，不要將空間受限的晶片包裝到LED蓋中，以提高其輻射硬度。 順便說一下，第一個是每公斤的價格。

It’s also worth noting helium nuclei (alpha particles) as a source of single event effects — not because there are some in solar radiation, but because plenty of alpha sources can be found in ordinary life, like led solder and some IC packaging materials. If you have heard about low-alpha bumps and underfills — it’s about single event mitigation in 「mundane」 applications not related to aerospace.

還值得一提的是，氦原子核(α粒子)是單事件效應的來源-並不是因為太陽輻射中有一些，而是因為在日常生活中會發現大量的α輻射源，例如led焊料和某些IC封裝材料。 如果您聽說過低阿爾法的顛簸和底部填充，那就是與航空航天無關的「平凡」應用中的單事件緩解。

Figure 2. A number of different particles spotted during the two-year mission in space. Quoted from: Xapsos et al., "Model for Cumulative Solar Heavy Ion Energy and Linear Energy Transfer Spectra", IEEE Transactions on Nuclear Science, Vol. 5, No. 6., 2007

圖2.在為期兩年的太空任務中發現的許多不同粒子。 引自：Xapsos等人，「累積太陽重離子能量和線性能量轉移譜的模型」，IEEE Transactions on Nuclear Science，第1卷。 5，第6號，2007年

1, 30 or 60 MeV * cm ^ 2/(mg) — how much is it? The upset threshold of a standard SRAM memory cell in the 7 nm technology is much lower than one, while for 180 nm it can vary from one to ten. The use of a special schematic allows to raise the threshold up to a hundred, but it is usually wiser to achieve 15 or 30 and to the rest via error-correcting codes. 60 MeV * cm ^ 2/(mg) can most often be found in requirements for destructive events — to ensure that the chip will highly likely survive its full intended lifespan.

1、30或60 MeV * cm ^ 2 /(mg)-多少？ 7納米技術中的標準SRAM存儲單元的翻轉閾值遠低於1，而180納米的閾值則可以從1改變為10。 使用特殊的原理圖可以將閾值提高到一百，但是通常更明智的做法是通過糾錯碼將閾值提高到15或30，然後達到其餘值。 60 MeV * cm ^ 2 /(mg)最經常出現在破壞性事件的要求中-以確保晶片極有可能在其預期的整個使用壽命中倖存下來。

位移損壞 (Displacement damage)

The displacement effects are local destruction of the crystal lattice due to an atom being "knocked out" of its intended place. The energy required for this is usually quite high, so most irradiating particles do not cause this effect. However, secondary irradiation can, and there are plenty of protons in space. These local lattice defects decrease charge carriers』 mobility, increase noise and do some other damage. Due to their very local nature, they normally do not significantly affect conventional CMOS chips — but they dominate in solar cells, photodetectors, power transistors and other devices based on compound semiconductors, such as gallium arsenide and gallium nitride. Transistors in compound semiconductors are usually not MOS, but JFET or HEMT, so they lack gate oxide. This explains their high total dose tolerance — they simply do not suffer from the effects causing the rapid degradation of CMOS chips. However, displacement effects are much more significant in these new materials, so they should be considered and weighted appropriately.

位移效應是由於原子「敲除」其預期位置而導致的晶格局部破壞。 為此所需的能量通常很高，因此大多數輻射粒子不會引起這種效果。 但是，可以進行二次輻照，並且空間中有很多質子。 這些局部晶格缺陷會降低電荷載流子的遷移率，增加噪聲並造成其他一些損害。 由於它們的局部特性，它們通常不會顯著影響傳統的CMOS晶片-但它們在太陽能電池，光電探測器，功率電晶體和其他基於化合物半導體的器件(例如砷化鎵和氮化鎵)中佔主導地位。 複合半導體中的電晶體通常不是MOS，而是JFET或HEMT，因此它們缺少柵極氧化物。 這解釋了它們的高總劑量耐受性-它們根本不會遭受導致CMOS晶片快速退化的影響。 但是，位移效應在這些新材料中更為重要，因此應考慮並適當權衡它們。

As we’re finished with the description of effects, let’s look at where and how they threaten integrated circuits.

完成對效果的描述後，讓我們看一下它們在哪裡以及如何威脅集成電路。

radhard IC的不同軌道和其他應用 (Different orbits and other applications of radhard ICs)

Figure 3. Total ionizing dose calculations, for ten years of satellite lifetime, under the shielding of 1 g/cm^2. Adapted from N. Kuznetsov, "Radiation danger on space orbits and interplanetary trajectories of satellites" (in Russian).

圖3.在1 g / cm ^ 2的屏蔽下，十年衛星壽命的總電離劑量計算。 改編自庫茲涅佐夫(N. Kuznetsov)，「衛星的空間軌道和行星際軌道上的輻射危險」( 俄語 )。

Figure 3 shows an example of total ionizing dose calculation for different orbits. There are multiple assumptions there — including solar activity, shape, material and thickness of protection, but you can get the idea: the dose rate can vary in five orders of magnitude at different orbits. At low orbits under the first Van Allen belt, the dose is absorbed so slowly that many out-of-the-shelf commercial chips can withstand several years in these conditions, like laptops at ISS do. Even much more fragile people can fly there for years without dramatic health consequences. Low orbits are extremely important as they encompass the entire manned astronautic, the Earth remote sensing, many present communication satellites and future internet-from-above constellations. Last but not least, almost all CubeSats are launched into low orbits.

圖3顯示了不同軌道總電離劑量計算的示例。 那裡有多種假設-包括太陽活動，形狀，材料和保護層的厚度，但是您可以理解：劑量率在不同的軌道上可以變化五個數量級。 在第一個Van Allen帶下的低軌道上，劑量吸收得如此緩慢，以至於許多現成的商用晶片在這種情況下都可以承受數年，就像ISS的筆記本電腦一樣。 甚至更脆弱的人也可以在那飛行很多年而不會造成嚴重的健康後果。 低軌道非常重要，因為它們涵蓋了整個載人航天，地球遙感，許多現有的通信衛星以及未來的網際網路之上的星座。 最後但並非最不重要的一點是，幾乎所有的CubeSat衛星都被送入低軌道。

低軌道 (Low orbit)

Actually, the importance of low orbits is the root of multiple speculations that expensive radiation hardened chips are not needed at all, and COTS can do everything if not rejected by the overly conservative industry. Yes, COTS can do some decent job, but there are some pitfalls, even at low orbits.

實際上，低軌道的重要性是多種猜測的根源，即根本不需要昂貴的輻射硬化晶片，而且如果過度保守的行業不拒絕，COTS可以做所有事情。 是的，COTS可以做一些體面的工作，但是即使在低軌道上也有一些陷阱。

The van Allen belts protect the Earth only from light particles, mainly solar electrons and protons. Heavier particles, even though they are much rarer, quietly reach even our last shield — the atmosphere — and cause single effects, including the catastrophic latchup capable of irreversibly destroying any chip at any moment. Therefore, commercial chips can be used only if they are somehow protected from the latchup, or the entire spacecraft can be lost.

範艾倫帶僅保護地球免受輕粒子(主要是太陽電子和質子)的侵害。 較重的粒子，即使它們稀少得多，也可以悄悄地到達我們的最後一道盾牌-大氣-並產生單一的影響，包括災難性的閂鎖，該閂鎖能夠在任何時候不可逆轉地破壞任何晶片。 因此，只有在某種程度上保護了商業晶片免受閂鎖，否則整個太空飛行器可能會丟失，才可以使用它們。

Another problem is that the chips used in space are not just processors and memory, but also many other types, including power and analogue ones. Radiation tolerance of non-logic circuits is much more complex, less investigated and less predictable. Moreover, modern SoCs contain a lot of non-digital blocks like PLL, ADC, I/O circuits. For example, the most common reason for flash memory total dose failure is the high-voltage generator used for memory writing. Analogue circuits suffer from offset increase, small leakages can significantly affect the functioning of low-power analogue, power transistors are experiencing breakdown voltage degradation, and so on and so on.

另一個問題是，空間中使用的晶片不僅是處理器和內存，而且還有許多其他類型，包括電源和模擬類型。 非邏輯電路的輻射容忍度要複雜得多，研究較少且難以預測。 此外，現代SoC包含許多非數字模塊，例如PLL，ADC，I / O電路。 例如，快閃記憶體總劑量失敗的最常見原因是用於存儲器寫入的高壓發生器。 模擬電路的失調增加，小洩漏會嚴重影響低功率模擬電路的功能，功率電晶體正遭受擊穿電壓降級等。

It’s also important to remember that radiation sensitivity is, well, sensitive to process variations, sometimes even small ones. So, if the fab changes the temperature of some oxide growing, you can throw your radiation testing results into a trash can. Commercial vendors never guarantee that the different batches of the same product will have the same crystal and that the manufacturing process will be stable for some long time. The processor from iPhone 6, Apple A9, was produced on both 16 nm TSMC and 14 nm Samsung fabs, and the user is ineligible to know which version is inside the specific cell phone. Such an approach is unfortunately impossible for high-reliability circuits, and that’s why radhard chips are often manufactured on some kinds of Trusted Foundries or at least on automotive-intended processes, as the car industry also cares about reliability and needs stable technology.

同樣重要的是要記住，輻射敏感性對Craft.io變化敏感，有時甚至很小。 因此，如果製造廠改變了某些氧化物生長的溫度，則可以將輻射測試結果扔到垃圾桶中。 商業供應商永遠不能保證同一產品的不同批次具有相同的晶體，並且製造過程將長期穩定。 iPhone 6，Apple A9的處理器是在16 nm TSMC和14 nm Samsung fab上生產的，用戶無資格知道特定手機內的哪個版本。 不幸的是，這種方法對於高可靠性電路是不可能的，這就是為什麼radhard晶片通常在某些類型的Trusted Foundry或至少在汽車預期的Craft.io上製造的原因，因為汽車行業還關心可靠性並需要穩定的技術。

其他軌道 (Other orbits)

However, satellites don’t fly just on low orbits. I will take a 「Molniya」 orbit as an example of very different requirements. This orbit is named after a Soviet satellite which was there first. 「There」 is a polar orbit with minimal altitude around 500 km and maximal around 40 000. The orbital period is twelve or twenty-four hour, and the satellite spends most of the time near apogee, acting as a pseudo-static object and providing communications for polar regions where geostationary satellites can’t be seen.

但是，衛星不僅會在低軌道上飛行。 我將以「莫利尼亞」軌道為例說明完全不同的要求。 該軌道以最早出現的蘇聯衛星命名。 「那裡」有一條極地軌道，其最小高度在500公裡左右，最大高度在4萬左右。軌道周期為十二或二十四小時，衛星大部分時間都在近地點附近，充當偽靜態物體並提供無法看到對地靜止衛星的極地通信。

Figure 4. Molniya orbit with hours marked. Taken from Wikipedia.

圖4.標記了小時數的摩利尼亞軌道。 取自維基百科。

The lifespan of the very first Molniya satellites was very short — just a handful of months. Primarily due to the degradation of solar panels powering radio transmitters. Why was the degradation so high? Perigee 500 km and apogee 40 000 km means that the satellite crosses van Allen belts twice each period — or four times per day. Van Allen belts gather and concentrate solar electrons and protons, so the environment there is among the worst one can have.

最早的Molniya衛星的壽命很短-僅幾個月。 主要是由於為無線電發射器供電的太陽能電池板的性能下降。 為什麼降解如此之高？ 近地點500公裡和遠地點40 000公裡，意味著衛星每個周期兩次穿過範艾倫帶-每天四次。 範艾倫帶聚集並聚集太陽能電子和質子，因此那裡的環境是最惡劣的環境之一。

Figure 1 promises the dose rate of some tens of kilorads per ten-year lifespan on high orbits and some hundreds of thousand if the satellite is in contact with van Allen belts. That’s higher than many commercial chips can achieve, so one will need significantly thicker, heavier and more expensive shielding to use them. It may still be cheaper than buying radiation hardened ICs, but here we descend into the world of satellite creation, which is out of this article’s scope. Let’s just say that shielding is heavy and therefore expensive to launch while it doesn’t solve all problems and can even make some of them worse.

圖1保證了在高軌道上每十年壽命約數十萬拉德的劑量率，如果衛星與範艾倫帶接觸，則約數十萬的劑量率。 這比許多商用晶片所能達到的要高，因此使用它們將需要明顯更厚，更重且更昂貴的屏蔽層。 它可能仍然比購買防輻射的IC便宜，但在這裡我們進入了人造衛星的世界，這不在本文的討論範圍之內。 我們只能說屏蔽很重，因此發射起來很昂貴，但不能解決所有問題，甚至會使其中一些問題變得更糟。

The ultimate answer to a question if COTS chips can be used in space is 「Yes, but」. There are many opportunities, but also many constraints. Also, if you want to use a COTS chip in your space-related project and invest in its radiation testing, stockpile your ten-year need. By the way, it’s a credible business-model: well-known and very respected company 3DPlus tests a lot of COTS chips chooses ones that are accidentally better than others and then packs them into their own hybrid modules found everywhere in space, including Curiosity Rover on Mars.

對於是否可以在太空中使用COTS晶片的問題，最終的答案是「是，但是」。 機會很多，但約束也很多。 另外，如果您想在與太空有關的項目中使用COTS晶片並投資其輻射測試，則可以存儲10年的需求。 順便說一句，這是一種可靠的商業模式：知名且備受推崇的公司3DPlus對許多COTS晶片進行了測試，選擇了偶然比其他晶片更好的晶片，然後將它們包裝到太空中隨處可見的自己的混合模塊中，包括好奇號流浪者在火星上。

軍用級和輻射硬度 (Military-grade and radiation hardness)

It’s impossible to avoid the topic of 「military-grade」 chips while dealing with preconceptions about radiation hardness. They are believed to be radiation hardened, but the real situation is a bit more complicated. Not all military-grade chips are radhard and not all radhard chips are military-grade. If we look into the US military standard Mil-Std-883, we will find there a lot of different environmental tests — for thermal cycling, humidity, air with sea salt, etc. etc.

在處理有關輻射硬度的先入之見時，不可避免地要避免使用「軍用級」晶片這一話題。 它們被認為可以防輻射，但是實際情況要複雜一些。 並非所有軍事級晶片都是radhard，也不是所有radhard晶片都是軍事級。 如果我們查看美國軍事標準Mil-Std-883，就會發現有很多不同的環境測試-用於熱循環，溼度，含海鹽的空氣等。

Radiation is addressed in the following paragraphs:

下列段落討論了輻射：

• 1017.2 Neutron irradiation

  1017.2中子輻照

• 1019.8 Ionizing radiation (total dose) test procedure

  1019.8電離輻射(總劑量)測試程序

• 1020.1 Dose rate induced latchup test procedure

  1020.1劑量率誘導的閂鎖測試程序

• 1021.3 Dose rate upset testing of microcircuits

  1021.3微電路劑量率不合格測試

• 1023.3 Dose rate response of linear microcircuits

  1023.3線性微電路的劑量率響應

Total dose? Check! Total dose rate? Check. Single events? Sorry, nothing to find here. Many specifications for military-grade radhard chips include the requirements for single event effects, but they are not part of the military standard. So, 「military-grade」 status does not guarantee that the chip will be capable to work in space, or at Large Hadron Collider. The best-known example of this misconception in action was the infamous Russian satellite called 「Phobos-Grunt」. It was sent to Mars in 2011, but never left Earth’s orbit. The official investigation concluded that the fatal failure occurred in American military-grade SRAM chip which some poor engineer found to be suitable for space travel while it wasn’t in fact protected from single event latchup.

總劑量？ 檢查！ 總劑量率？ 檢查一下 單項活動？ 抱歉，在這裡找不到任何內容。 軍用級radhard晶片的許多規範都包括對單事件效果的要求，但它們不是軍用標準的一部分。 因此，「軍用級」狀態不能保證晶片能夠在太空或大型強子對撞機上工作。 這種誤解在行動中最著名的例子是臭名昭著的俄羅斯衛星「 Phobos-Grunt」。 它於2011年被送往火星，但從未離開地球軌道。 官方調查得出的結論是，致命故障發生在美國軍用級SRAM晶片上，一些可憐的工程師發現該晶片適合於太空旅行，而實際上卻沒有受到單事件閂鎖的保護。

Recent SEE testing of 1M and 4M monolithic SRAMs at Brookhaven National Laboratories has shown an extreme sensitivity to single-event latchup (SEL). We have observed SEL at the minimum heavy-ion LET available at Brookhaven, 0.375 MeV-cm2/mg

Brookhaven國家實驗室最近對1M和4M單片SRAM的SEE測試表明，它對單事件閂鎖(SEL)具有極高的敏感性。 我們已經在布魯克海文獲得的最小重離子LET下觀察到SEL，0.375 MeV-cm2 / mg

says the report on that very chip. The report was published in 2005, but wasn’t taken into account by 「Phobos-Grunt」 designers, who just supposed that 「military-grade」 is enough to fly to the Red planet.

那個晶片上的報告說。 該報告於2005年發布，但「 Phobos-Grunt」設計人員並未考慮到該報告，他們只是認為「軍事級」足以飛往紅色星球。

平凡的應用 (Mundane applications)

The importance of radiation hardness is not limited to space and military applications. The atmosphere works as the final shield between the space radiation and the life on Earth, but also creates secondary particles, which are aplenty at the airliner heights (a typical transatlantic flight can see a dozen of single event upsets in the onboard computer). Some secondary particles even reach the ground and are seen in the devices with the highest memory sizes — like supercomputers. X-ray radiation is routinely used in medicine, and radiotherapy is an important way to combat malignant tumours. More and more electronics are needed in medical devices, and these areas aren't an exception.

輻射硬度的重要性不僅限於太空和軍事應用。 大氣層是空間輻射與地球生命之間的最終屏障，但還會產生次級粒子，這些粒子在客機高度上非常豐富(典型的跨大西洋飛行可以在機載計算機上看到許多單事件擾動)。 一些次級粒子甚至到達地面，並在具有最大內存大小的設備(例如超級計算機)中看到。 X射線通常在醫學中使用，放射療法是對抗惡性腫瘤的重要方法。 醫療設備中需要越來越多的電子設備，這些領域也不例外。

And, of course, we should not forget that all the fuss with lead-free solder was partially caused by the fact that lead and some other materials used in IC fabrication contain impurities of heavy elements like uranium. The use of these materials cause the generation of a small, but still well-measurable flux of alpha particles — right around vulnerable silicon. In the case of BGA packages or 3D assemblies — over the entire surface of vulnerable silicon.

而且，當然，我們不應該忘記，無鉛焊料的所有問題都部分是由於鉛和IC製造中使用的某些其他材料包含重元素(如鈾)的雜質造成的。 這些材料的使用會導致在易損矽周圍產生少量但仍可測量的α粒子通量。 對於BGA封裝或3D組件-在易損矽的整個表面上。

Luckily, alpha particles have a rather short ionization track (just a few microns, depending on energy), and multi-layer metallization helps to reduce their influence. The bad news is that at low process nodes the required energy is so small that all alpha particles, which are able to reach the surface, cause upsets. For example, TSMC published an article at the 2018 IEEE International Reliability Physics Symposium, measuring the number of alpha-related upsets in 7 nm SRAM. So, the problem still exists in a largely lead-free world.

幸運的是，α粒子具有相當短的電離軌跡(取決於能量，僅幾微米)，多層金屬化有助於減少其影響。 壞消息是，在低Craft.io節點處，所需的能量是如此之小，以至於所有能夠到達表面的α粒子都會引起不安。 例如，臺積電(TSMC)在2018年IEEE國際可靠性物理研討會上發表了一篇文章，測量了7 nm SRAM中與alpha相關的翻轉次數。 因此，在很大程度上無鉛的世界中仍然存在該問題。

Figure 5. Solder bumps as the alpha radiation source. Image courtesy of Mitsubishi Materials.

圖5.焊料凸點作為α輻射源。 圖片由三菱綜合材料提供 。

I also want to say a few words on yet another application of radiation hardened chips: high energy physics and nuclear industry. Hadron colliders and nuclear power plants require extremely robust electronics capable of working in contaminated active zones for many years. The same would be the case for robots designed to deal with nuclear-related catastrophes like Chernobyl or Fukushima. TID requirements for these circumstances could be dozens or even hundreds of Megarads (Si), which is three orders of magnitude more than in conventional space applications. The problem is further complicated by the fact that such durability is required not just from digital ICs, but also from power management and analog chips, which could be found in multichannel telemetry systems and servo motor drives. These chips could be much more vulnerable than digital ICs in terms of their reaction to transistor degradation. TID behaviour and hardening of digital circuits is well-investigated and well understood, but for analog circuits, it’s much more interesting as every case and every circuit may require an individual approach rather than a semi-automated application of known methods. The electric circuit is often guarded know-how in analog design, and it’s more true for radhard analog.

我也想談談輻射硬化晶片的另一種應用：高能物理和核工業。 強子對撞機和核電站需要極其堅固的電子設備，這些電子設備必須能夠在受汙染的活動區域中工作多年。 設計用於應對車諾比核電站或福島核電站核災難的機器人也是如此。 在這種情況下，TID要求可能為數十甚至數百兆拉(Si)，這比常規太空應用要大三個數量級。 由於不僅需要數字IC還需要這種耐用性，而且還需要電源管理和模擬晶片來提供這種耐用性，這一問題變得更加複雜，在多通道遙測系統和伺服電機驅動器中都可以找到這種耐用性。 就其對電晶體退化的React而言，這些晶片可能比數字IC更加脆弱。 TID行為和數字電路的強化已經得到了充分的調查和很好的理解，但是對於模擬電路，它更有趣，因為每種情況和每種電路都可能需要單獨的方法，而不是已知方法的半自動化應用。 電路在模擬設計中通常是受保護的專有技術，對於radhard模擬而言更是如此。

Figure 6. Normal and radiation hardened bandgap voltage reference. Taken from Y. Cao et al., «A 4.5 MGy TID-Tolerant CMOS Bandgap Reference Circuit Using a Dynamic Base Leakage Compensation Technique», IEEE Transactions on Nuclear Science, Vol.60, No.4, 2013

圖6.正常和輻射硬化的帶隙電壓基準。 摘自Y. Cao等人的《使用動態基極洩漏補償技術的A 4.5 MGy耐TID CMOS帶隙基準電路》，IEEE核科學學報，第60卷，第4期，2013年

Let's look at a good (and rare) example of such a task. Bandgap reference voltage source is a simple and well-known circuit that could be found in any analog IC. This circuit normally contains a pair of bipolar transistors controlled by an operational amplifier. These bipolars show significant leakage under irradiation, and this leakage leads to significant output voltage changes, sometimes 10-20% under high doses, which corresponds to the effective ADC resolution of two to three bits. The circuit at the right shows reference voltage variation within 1% (which gives us more than 7 bits) under the total dose of 4.5 MGy. As you may see, it wasn’t easy to achieve this outstanding result: local feedbacks are scattered everywhere, subtracting base current from the equation and therefore getting rid of leakage current too. This radhard version contains four times more transistors and has two times more power consumption than its conventional analog. The worst is that, as I』ve said, every circuit normally requires an individual approach, making analog radhard designer's work very challenging. And there’s also a single event effects problem, solution for which is as well badly formalized and very circuit-dependent.

讓我們看一下此類任務的一個好例子(很少見)。 帶隙基準電壓源是一種簡單且眾所周知的電路，可以在任何模擬IC中找到。 該電路通常包含一對由運算放大器控制的雙極電晶體。 這些雙極型器件在輻照下顯示出明顯的洩漏，這種洩漏導致顯著的輸出電壓變化，有時在高劑量下會發生10-20％的變化，這相當於2到3位的有效ADC解析度。 右邊的電路顯示在4.5 MGy的總劑量下，參考電壓變化在1％以內(給我們提供了超過7位)。 如您所見，要獲得如此出色的結果並不容易：局部反饋分散在各處，從等式中減去基極電流，因此也消除了洩漏電流。 該radhard版本的電晶體數量是其常規模擬產品的四倍，功耗也要高出兩倍。 最糟糕的是，正如我已經說過的，每個電路通常都需要一種單獨的方法，這使得模擬radhard設計人員的工作非常具有挑戰性。 此外，還有一個單一的事件影響問題，其解決方案形式化很差且與電路密切相關。

輻射硬度和Craft.io節點 (Radiation hardness and process node)

The website of one established microelectronics fab with old links to the aerospace industry for a long time contained a statement that radiation tolerance could not be achieved at process nodes below 600 nm, as 「charged particles pierce silicon and destroy transistors」. Surprisingly, but likely unrelated, the minimal available process node for that fab, whose high-ranking official said in the interview that it’s 「technologically impossible」 to create radiation hardened ICs at nodes lower than 90 nm. You may guess what was the minimal node at that fab. I was quite surprised to read that interview as I was working on a radhard 65 nm chip at that moment. I can understand some marketing nonsense, but such words are dangerous in the long term, especially when said to the wide audience or to the audience of decision-making persons.

一家建立了很久的微電子製造廠的網站已經很長時間了，它與航空航天業有著很長的聯繫，該網站的聲明中說，在「低於600 nm的Craft.io節點」上無法達到輻射耐受性，因為「帶電粒子會刺穿矽並破壞電晶體」。 令人驚訝的是，但可能與之無關的是，該晶圓廠的最小可用Craft.io節點，其高級官員在接受採訪時表示，「在技術上不可能」在低於90 nm的節點上製造輻射硬化IC。 您可能會猜到那個晶圓廠的最小節點是什麼。 當我當時正在研究radhard 65 nm晶片時，我很驚訝地讀到這篇採訪。 我可以理解一些營銷上的胡說八道，但是從長遠來看，這樣的用語很危險，尤其是對廣大受眾或決策者的受眾而言。

I also regularly see the reasoning that ICs built on coarse process nodes are SEL-immune due to very high energy required to influence transistors, so the long-time use of proven technology is not just justified, but simply necessary. Or vice versa, sub-something process nodes work with very low supply voltages — too low to exhibit SEL as parasitic thyristor simply can’t open. Or there are opinions that the problem is not in process nodes, it’s CMOS technology that is fundamentally weak (as evidenced by some tests done by the applicant in early seventies), while in good old time radhard ICs were bipolar/SOI/GaAs. So, since CMOS technology is fundamentally flawed, there is no other way than to continue using ancient tech for spaceships. Preferably, electronic lamps.

我還經常看到這樣的理由，由於影響電晶體的能量非常高，因此在粗糙的Craft.io節點上構建的IC不受SEL的影響，因此長期使用成熟的技術不是合理的，而是很必要的。 反之亦然，子級Craft.io節點可在非常低的電源電壓下工作-太低而無法展示SEL，因為寄生晶閘管根本無法打開。 或者有觀點認為問題不在於Craft.io節點，而在於CMOS技術從根本上是薄弱的(如申請人在七十年代初所做的一些測試所證明的)，而在較早的時期，radhard IC是雙極性/ SOI / GaAs。 因此，由於CMOS技術從根本上來說是有缺陷的，因此除了繼續將古老的技術用於宇宙飛船之外，別無他法。 優選地，電子燈。

「 Radhard」等於「舊」？ ("Radhard" equals "old"?)

For the sake of justice, some old ICs built on multi-micron process nodes are really insensitive to single events. But 「some」 doesn’t mean 「all」, and all kinds of problems were documented through the history of space exploration. Large process nodes understandably require a lot of energy from ionizing particle fo flip a bit — but they also require the same amount of energy at each switching during normal operation, so I wish a lot of luck to anyone willing to build an Intel Core processor equivalent out of 74-series logic and I would love to see a rocket that would be able to lift such a monster into the air.

為了公正起見，一些建立在微米Craft.io節點上的舊IC確實對單個事件不敏感。 但是「一些」並不意味著「全部」，並且通過太空探索的歷史記錄了各種問題。 可以理解，大型過程節點需要一點點電離粒子的翻轉才能消耗大量能量，但是在正常運行期間，每次切換它們也需要相同量的能量，因此，我希望對願意構建與之等效的Intel Core處理器的所有人感到好運從74系列邏輯中脫穎而出，我很想看到一枚​​能夠將這種怪獸升空的火箭。

On the other hand, microelectronics is not limited to microprocessors and memory. There is a huge variety of tasks where latest process nodes are not necessary, unprofitable or simply unsuitable. The global market for IC built on 200 mm wafers (process node 90 nm and above) has been growing for several years, up to a periodic shortage of production equipment. 「Outdated」 fabs produce both old and new designs, and many manufacturing companies are commercially successful despite not being on par with TSMC and Samsung. So, take all process node fuss with a grain of salt when data processing isn’t the topic.

另一方面，微電子不限於微處理器和存儲器。 有許多任務不需要最新的過程節點，無利可圖或根本不合適。 基於200毫米晶圓(Craft.io節點90納米及以上)構建的IC的全球市場已經增長了幾年，直至生產設備的周期性短缺。 「過時」的晶圓廠生產新舊設計，儘管與臺積電和三星不相上下，但許多製造公司在商業上都取得了成功。 因此，當數據處理不是主題時，請對所有過程節點大驚小怪。

Other factors inciting the use of older process nodes in aerospace are a longer life cycle of such products, expensive certification and small production quantities. The design of a simple 180 nm IC could cost a few million Euro, and when these millions plus few more millions required for certification and testing are divided by a thousand ICs, each of these ICs becomes very expensive. And what if we need to recoup a few hundred millions for a 7-5 nm design? These troubles lead to two things. First, the design of most radiation hardened ICs in the world is government-subsidized. Second, successful designs are manufactured as long as it’s possible, and IPs from them are reused and reused and reused to lower costs, forcing the manufacturer to stay at the proved process node. These factors combined could create an illusion that most radhard ICs are outdated. The clients also support proven projects, or, to be more precise, flight-proven projects. If a chip has a heritage in space, it’s a colossal competitive advantage, and you may be sure that this advantage is exploited as long as possible, even when the design itself becomes outdated.

促使在航空航天中使用較舊的過程節點的其他因素是此類產品的使用壽命更長，認證費用昂貴且生產量少。 一個簡單的180 nm IC的設計可能要花費幾百萬歐元，而當數以百萬計的認證和測試所需的數百萬美元除以一千個IC時，這些IC中的每一個都會變得非常昂貴。 如果我們需要為7-5 nm設計賠償幾億美元呢？ 這些麻煩導致兩件事。 首先，世界上大多數輻射硬化IC的設計都是由政府補貼的。 第二，成功的設計要儘可能地進行製造，而來自它們的IP可以重複使用，再利用和再利用以降低成本，從而迫使製造商留在經過驗證的過程節點上。 這些因素加在一起可能會造成大多數radhard IC已過時的幻覺。 客戶還支持經過驗證的項目，或更準確地說，是經過飛行驗證的項目。 如果晶片在太空中具有傳統，那將是一項巨大的競爭優勢，即使設計本身已經過時，您也可以確保儘可能多地利用這一優勢。

The public image of radhard ICs is then further diminished by the fact that the most famous of them are used in long-term scientific missions. In 2015, I』ve seen a lot of news like 「the New Horizons has the same CPU as 20-year-old original Sony Playstation」. Well said, well said. The New Horizons was launched in 2006, its development had begun in 2000 — it was the year of the first flight of the processor they used. Mongoose-V processor shares the MIPS ISA with PlayStation's MIPS R3000, but it’s entirely different chip released in 1998, some eight years before the launch of the New Horizons and seventeen years before it was featured in the news. Here is another example: Power750 processors came out for commercial applications in 1997, particularly for iMac computers. Their radhard counterpart, RAD750, was released in 2001 and flown into space in 2005, four years later. It was the highest computational power available for the Curiosity Mars Rover, so there was a lot of news about an ancient processor on Mars later in 2012. And, to make it even funnier, almost the entire Curiosity design was reused for the Perseverance, which is due to produce more stupid processor-related news headlines next year.

由於最著名的radhard IC用於長期科學任務，因此進一步降低了radhard IC的公眾形象。 在2015年，我看到了很多新聞，例如「 New Horizo​​ns與擁有20年歷史的原始Sony Playstation具有相同的CPU」。 說得好，說得好。 New Horizo​​ns於2006年推出，其開發工作於2000年開始-這是他們使用的處理器首次飛行的一年。 Mongoose-V處理器與PlayStation的MIPS R3000共享MIPS ISA，但它與1998年發布的晶片完全不同，這是在New Horizo​​n發布之前大約8年，而在新聞發布之前已是17年。 這是另一個示例：Power750處理器於1997年投入商業應用，尤其是iMac計算機。 他們的radhard對應機RAD750於2001年發布，並於四年後於2005年飛入太空。 這是「好奇號」火星探測器所具有的最高計算能力，因此在2012年晚些時候有很多關於火星上的古老處理器的消息。而且，更有趣的是，幾乎整個「好奇號」設計都被重新用於「恆心」計劃，明年將產生更多與處理器相關的愚蠢新聞頭條。

「 Radhard」等於「新」？ ("Radhard" equals "new"?)

Despite all of the above, the newest radhard ICs of today are designed at the nodes between 45 and 20 nm, like fresh radhard Xilinx Kintex FPGAs. American RAD5500 series is manufactured at 45 nm, European DAHLIA, which is due in 2021, uses 28 nm, and so on. GlobalFoundries already offers a 12 nm process for aerospace applications, so the modern radhard ICs are definitely modern.

儘管有上述所有內容，但今天的最新radhard IC是在45至20 nm之間的節點上設計的，就像新鮮的radhard Xilinx Kintex FPGA一樣。 美國RAD5500系列以45 nm製造，歐洲DAHLIA將於2021年製造，使用28 nm，依此類推。 GlobalFoundries已經為航空航天應用提供了12 nmCraft.io，因此現代radhard IC絕對是現代的。

There are many topics to be researched and there is no shortage of scientific articles on the topic of radiation hardness of modern technologies as new challenges tend to emerge with each new generation. Process node shrinking definitely affects radiation hardness, but this effect is complex and not necessarily negative. The general trend is that TID influence decreases while the role of single events becomes more important. Thinner gate oxides lead to smaller threshold voltage shifts, but then these gate oxides are not silicon oxide anymore, and their interface with silicon is different, and so on and so on.

有很多課題需要研究，關於現代技術的輻射硬度這一主題的科學文章也不乏，因為每一代人都面臨著新的挑戰。 Craft.io節點的收縮肯定會影響輻射硬度，但是這種影響是複雜的，不一定是負面的。 總體趨勢是，TID影響減小，而單個事件的作用變得更重要。 較薄的柵極氧化物會導致較小的閾值電壓漂移，但是這些柵極氧化物不再是氧化矽，它們與矽的界面也不同，依此類推。

Figure 7. Two versions of radiation hardened inverter. Taken from Vaz et al., "Design Flow Methodology for Radiation Hardened by Design CMOS Enclosed-Layout-Transistor-Based Standard-Cell Library", Journal of Electronic Testing, volume 34, 2018

圖7.兩種版本的防輻射逆變器。 取自Vaz等人，「通過基於設計CMOS封閉布局電晶體的標準單元庫對輻射進行硬化的設計流方法論」，電子測試雜誌，第34卷，2018年

Figure 7 shows two implementations of an inverter. On the right, we see a complete stuffing — enclosed layout transistors to combat total dose and individual guard rings against Inter-transistor leakages and SEL. On the right — a simpler design for lower total dose requirements: transistors are linear. It’s worth noting that total dose tolerance of 50-100 krad(Si) is quite sufficient for many space applications, and normal linear transistors do an excellent job there while saving area, not suffering from aspect ratio limitation and having better matching than ELTs. Also note that only nMOSFETs suffer from source-drain leakage and only they have to have enclosed gates if high total dose tolerance is needed, but pMOSFETs are often drawn as ELTs too for easier size balancing between nMOS and pMOS.

圖7顯示了逆變器的兩種實現。 在右側，我們看到了一個完整的填充物-封閉的布局電晶體以抵抗總劑量，並設有單獨的保護環以防止電晶體間洩漏和SEL。 右側-一種用於降低總劑量的更簡單設計：電晶體為線性。 值得注意的是，50-100 krad(Si)的總劑量容限對於許多空間應用來說已經足夠了，普通的線性電晶體在節省空間的同時也做得很好，而不會受到長寬比的限制，並且比ELT具有更好的匹配性。 還要注意的是，只有nMOSFET受源漏洩漏的困擾，如果需要高的總劑量容限，則只有封閉的柵極，但為了使nMOS和pMOS之間的尺寸平衡更加容易，pMOSFET也經常被用作ELT。

Single events』 relationship with process nodes is more interesting. Approximate diameter of the charge collection area of an ionizing particle hit is around one micron — which is much bigger than the size of memory cells in deep submicron process nodes. And indeed, experiments show multiple bit upsets from a single ion strike.

單個事件與流程節點的關係更加有趣。 電離粒子撞擊的電荷收集區域的近似直徑約為1微米-遠大於深亞微米Craft.io節點中存儲單元的大小。 實際上，實驗表明，一次離子撞擊會造成多個位不安。

Figure 8. Multiple bit upsets in two different 6T SRAM cell arrays. Taken from M. Gorbunov et al., "Design of 65 nm CMOS SRAM for Space Applications: A Comparative Study", IEEE Transactions on Nuclear Science, Vol.61, No.4, 2014

圖8.兩個不同的6T SRAM單元陣列中的多個位翻轉。 取自M. Gorbunov等人，「用於太空應用的65 nm CMOS SRAM設計：比較研究」，IEEE Transactions on Nuclear Science，第61卷，第4期，2014年

Figure 8 shows the experimental data on single-event upsets in 65 nm bulk technology. On the left — normal commercial 6T-SRAM design. Ten upsets from the single hit! Hamming code won’t protect you from such disaster. So, when we’re talking about commercial ICs, coarse process nodes are somewhat better than smaller ones, as they will mostly experience easier to correct single-bit upsets. But when we’re designing a radhard chip form the scratch, there are a plethora of architectural, schematic and layout solutions capable to produce both high single event tolerance and high performance. The right side of figure 8 also shows the results from 6T-SRAM, from the same die, with the same schematic, but with a different layout. The price of getting rid of most multiple bit upsets, latchup and for increasing total dose hardness is very simple: four times area increase. Doesn’t sound nice, but no one said it would be easy. However, if you’re ready for compromises, Radiation Hardening by Design allows achieving any predetermined level of radiation hardness at any bulk technology.

圖8顯示了65 nm批量技術中單事件翻轉的實驗數據。 左側-常規商用6T-SRAM設計。 單打十下！ 漢明代碼無法保護您免受此類災難的影響。 因此，當我們談論商用IC時，粗製程節點要比較小的製程節點好一些，因為它們通常會更容易糾正單位位失調。 但是，當我們從頭開始設計radhard晶片時，有大量的體系結構，原理圖和布局解決方案能夠產生高單事件容忍度和高性能。 圖8的右側還顯示了來自6T-SRAM的結果，該結果來自相同的管芯，相同的原理圖，但布局不同。 擺脫大多數多位打亂，閂鎖和增加總劑量硬度的價格非常簡單：面積增加四倍。 聽起來不太好，但是沒有人說這很容易。 但是，如果您準備妥協，則可以通過任意設計的輻射硬化設計，以任何預定的技術達到任何預定水平的輻射硬度。

Why predetermined? Because different requirements could be satisfied with different means. But why not apply all of them at once and be fine for every possible application? Most radiation hardening methods normally come at the cost of compromising functional parameters to some extent (supply current, area, speed, etc.). Therefore overengineering will lead to non-competitive products. Sure, such low-volume ICs are rarely made for just one application and should be flexible, but detailed and reasonable radiation requirements are absolutely vital for the successful design.

為什麼要預定？ 因為用不同的方法可以滿足不同的要求。 但是，為什麼不一次全部應用它們，並適合每種可能的應用呢？ 通常，大多數輻射硬化方法都會以某種程度損害功能參數(電源電流，面積，速度等)為代價。 因此，過度設計將導致產品缺乏競爭力。 當然，這樣的小批量集成電路很少會只為一種應用而製造，而是應該具有靈活性，但是詳細而合理的輻射要求對於成功的設計絕對至關重要。

絕緣體上矽(SOI) (Silicon on Insulator (SOI))

The eye of the attentive reader could』ve caught the word 「bulk」 in the phrase 「predetermined level of radiation hardness at any bulk technology」. Isn’t it superfluous there? Isn’t it even wrong? It’s widely supposed that all the best radhard ICs are fabricated using 「silicon on insulator」 or 「silicon on sapphire」 technology. Right?

細心的讀者可以在「任何批量技術中的預定輻射強度水平」一詞中發現「散裝」一詞。 那裡不是多餘的嗎？ 甚至不對嗎？ 人們普遍認為，所有最好的radhard IC都是使用「絕緣體上的矽」或「藍寶石上的矽」技術製造的。 對？

The 「silicon on insulator」 technology has long been firmly entrenched with 「inherently radiation-hard」 fame. The roots of this popular fallacy go back into antiquity, when its predecessor, SOS (silicon on sapphire) was actively used for military designs. Why? Transistors in SOS/SOI are electrically separated from each other and from the substrate. This means much lower radiation-induced charge collection volume, which is quite handy for dealing with high dose rate events as it significantly reduces the chip shutdown time right after the nearby nuclear explosion — indeed an important trait for a product designed during the Cold War.

長期以來，「絕緣體上的矽」技術已經以「固有的抗輻射性」聲名遠揚。 這種流行謬論的根源可以追溯到上古時代，當時其前身SOS(藍寶石上的矽)被積極地用於軍事設計。 為什麼？ SOS / SOI中的電晶體相互之間以及與基板之間均電隔離。 這意味著輻射引起的電荷收集量要低得多，這對於處理高劑量率事件非常方便，因為它可以顯著減少附近核爆炸後的晶片關閉時間，這對於冷戰期間設計的產品而言確實是一個重要特徵。

Another part of the 「SOI = Radhard」 myth is insensitivity to latchup, including dose rate latchup. Latchup (also known as 「thyristor effect」) is one of the main headaches for spaceborne systems』 designers as it’s unpredictable and catastrophic. So the technology allowing to deal with it for free could be naturally considered a heavens』 gift. But the whole picture is a little bit more complicated.

「 SOI = Radhard」神話的另一部分是對閂鎖不敏感，包括劑量率閂鎖。 閂鎖(也稱為「晶閘管效應」)是星載系統設計人員的主要難題之一，因為它不可預測且具有災難性。 因此，允許免費處理的技術自然可以視為天賜之禮。 但是整個情況要複雜一些。

Figure 9. CMOS technology cross-section with parts of parasitic thyristor causing the latchup.

圖9. CMOS技術截面圖，其中部分寄生晶閘管引起閂鎖。

The cause of the latchup effect is the parasitic thyristor structure present in bulk CMOS technology. If the resistances Rs and Rw are large enough, a hit of an ionizing particle can deposit enough charge to open parasitic thyristor and create a short between supply and ground. How big are these resistances in real chips? The answer is quite simple: contact to substrate or well means an extra area, so their number is usually minimized to make chips cheaper. This means that a random commercial IC is more likely to be vulnerable to latchup than not. Latchup, however, can occur not just after an ion strike, but also due to ESD, high temperature, excessive current density or a door being shut in the nearby room, so automotive and industrial IC designers are familiar with the topic and more likely to take measures against it.

閂鎖效應的原因是體CMOS技術中存在的寄生晶閘管結構。 如果電阻Rs和Rw足夠大，則電離粒子的撞擊會沉積足夠的電荷來打開寄生晶閘管，並在電源和地之間造成短路。 這些電阻在實際晶片中有多大？ 答案很簡單：與基板或Kong的接觸意味著額外的面積，因此通常將其數量最小化以使晶片更便宜。 這意味著，隨機商用IC更有可能遭受閂鎖攻擊。 但是，閂鎖不僅可能發生在離子撞擊之後，還可能由於ESD，高溫，過大的電流密度或附近房間的門被關閉而引起，因此汽車和工業IC設計人員很熟悉該主題，並且更有可能這樣做。採取措施。

A chip can be driven off of the latchup condition by supply reboot, and such a reboot is quite acceptable in many space applications, so many commercial products can still be used in space — even if with some caution. So-called latchup current limiters are very popular in radhard systems, especially in ones requiring high computational performance impossible with up-to-date radhard processors. But such a solution has many limitations. Power reset is not always possible as there is no shortage in real-time calculations. The reboot during an important manoeuvre can put an end to a long mission. The current consumption of a modern IC may vary in a few orders of magnitude according to its working mode, so current consumption in the 「nothing happens and there is a latch」 state may be less than in high-performance normal condition. Where to set the current limit for such a chip? The required system reaction time also depends on a protected chip as some of them are very vulnerable and others can sustain thousands of latchups if they are being reset sufficiently fast.

可以通過重新啟動電源來使晶片脫離閂鎖狀態，並且這種重新啟動在許多航天應用中是完全可以接受的，因此即使有一些謹慎，仍然可以在航天中使用許多商用產品。 所謂的閂鎖電流限制器在radhard系統中非常流行，尤其是在那些需要最新radhard處理器無法實現的高計算性能的系統中。 但是這種解決方案有很多局限性。 並非總是可以進行電源重置，因為實時計算並不缺乏。 在重要的演習中重新啟動可能會結束漫長的任務。 現代IC的電流消耗可能會根據其工作模式而在幾個數量級上變化，因此「什麼也沒有發生並且有閂鎖」狀態的電流消耗可能會比高性能正常情況下的電流消耗少。 在哪裡設置這種晶片的電流限制？ 所需的系統響應時間還取決於受保護的晶片，因為其中一些晶片非常容易受到攻擊，而如果它們被足夠快地復位，則其他晶片可以承受數千個閂鎖。

If a chip is fabricated on SOI technology, all these problems are not a concern anymore. And no protection circuitry is necessary — completely nothing. That’s why commercial SOI chips are so attractive for space applications. For example, the new American spacecraft Orion is controlled by a commercial SOI-based microprocessor PowerPC 750 rather than its radhard version RAD 750.

如果採用SOI技術製造晶片，那麼所有這些問題都不再是問題。 無需保護電路-完全不需要。 這就是為什麼商用SOI晶片在太空應用中如此具有吸引力的原因。 例如，新型美國太空飛行器Orion由商用的基於SOI的微處理器PowerPC 750而不是其radhard版本RAD 750控制。

Figure 10. Leakage paths in bulk CMOS technology. Taken from J. Schwank et al., «Radiation effects in MOS oxides», IEEE Transactions on Nuclear Science, Vol. 55, No. 4, 2008

圖10.批量CMOS技術中的洩漏路徑。 摘自J. Schwank等人的《 MOS氧化物中的輻射效應》，IEEE Transactions on Nuclear Science，第1卷。 55，第4號，2008年

Then what’s the problem? There is not just a latchup, but also other radiation effects, and SOI is not inherently better than bulk technology in terms of both TID and SEE hardness. Figure 10 shows two leakage paths in bulk CMOS technology. Both of these paths are easily closed with proper layout design — one using ring n-channel transistors, the second — with the help of guard rings. These solutions have drawbacks from the point of view of the functioning of the circuit (restrictions on the minimum size of the ring transistor, area loss when using guard rings), but from the point of view of ensuring radiation resistance, they are very effective.

那是什麼問題 不僅存在閂鎖問題，還存在其他輻射影響，並且就TID和SEE硬度而言，SOI並非天生比本體技術更好。 圖10顯示了批量CMOS技術中的兩條洩漏路徑。 這兩種路徑都可以通過適當的布局設計輕鬆閉合-一種是使用環形n溝道電晶體，另一種是在保護環的幫助下。 從電路的功能的觀點來看，這些解決方案具有缺點(限制環形電晶體的最小尺寸，使用保護環時的面積損失)，但是從確保抗輻射性的觀點來看，它們是非常有效的。

Figure 11. SOI buried oxide leakage path. Taken from J. Schwank et al., "Radiation effects in MOS oxides", IEEE Transactions on Nuclear Science, Vol. 55, N.4, 2008

圖11. SOI掩埋氧化物洩漏路徑。 取自J. Schwank等人，「 MOS氧化物中的輻射效應」，IEEE Transactions on Nuclear Science，第1卷。 55，N.4，2008

In SOI technology, there is another leakage path from the source to the drain along the boundary of silicon and latent oxide. Hidden oxide is much thicker than the gate, which means that it can accumulate a lot of positive charge. If we consider the "lower" transistor (the right part of Figure 11), for which the hidden oxide is a gate, we will see that in a normal situation, the source-gate voltage of this transistor is zero and its threshold voltage is several tens of volts, i.e. the current through this transistor does not flow. When irradiated, a positive charge is accumulated in the hidden oxide (this process is influenced by the geometry of the main transistor, in particular, by the thickness of the silicon instrument layer), and the threshold voltage of the 「lower」 n-channel transistor drops. As soon as it falls below zero, the current begins to flow freely through the transistor along the uncontrolled bottom channel. Thus, from the point of view of the total absorbed dose, the SOI technology is fundamentally strictly worse than the volumetric technology. But maybe there is a way to fix the situation somehow?

在SOI技術中，沿著矽和潛在氧化物的邊界從源極到漏極還有另一條洩漏路徑。 隱藏的氧化物比柵極厚得多，這意味著它可以積累很多正電荷。 如果我們考慮「下層」電晶體(圖11的右半部分)，其中隱藏的氧化物是柵極，我們將看到，在正常情況下，該電晶體的源極-柵極電壓為零，而其閾值電壓為幾十伏，即不流過該電晶體的電流。 受到輻射時，正電荷會在隱藏的氧化物中積累(此過程受主電晶體的幾何形狀，特別是矽儀器層的厚度的影響)和「下部」 n溝道的閾值電壓電晶體滴。 一旦降到零以下，電流就開始沿著不受控制的底部通道自由流過電晶體。 因此，從總吸收劑量的角度來看，SOI技術從根本上說比體積技術要差。 但是也許有某種方法可以解決這種情況？

The substrate is usually grounded (in fact, connected to the lowest available potential), but in SOI nothing prevents us from setting negative voltage there and closing that parasitic back gate. This idea is, in fact, actively used — and in FDSOI technologies active back gate control is even used in their normal operation to minimize leakages in low-power modes and maximize speed when necessary. However, there is a catch: when we apply a high electric field to the buried oxide, we don’t just close the back transistor, but also accelerate the accumulation of positive charge. As a result, depending on technology specifics and the magnitude of the voltage applied, it’s possible that the total dose hardness will become even worse! There are other details, but in general, it’s possible to achieve almost any TID hardness level using standard CMOS technology, but there are some fundamental limitations for SOI. These limitations are normally negligible for low-orbit space applications, but if we’re speaking about multi-Megarad levels that could be present in the nuclear industry, commercially unfeasible technology changes are necessary for SOI.

基板通常接地(實際上，已連接到最低可用電位)，但是在SOI中，沒有什麼可以阻止我們在此處設置負電壓並關閉該寄生背柵。 實際上，這個想法已經得到了積極的運用，並且在FDSOI技術中，主動背柵控制甚至在其正常操作中也被使用，以最小化低功耗模式下的洩漏並在必要時最大化速度。 但是，有一個陷阱：當我們向埋入的氧化物施加高電場時，我們不僅會關閉後電晶體，還會加速正電荷的積累。 結果，取決於技術細節和所施加電壓的大小，總劑量硬度可能會變得更糟！ 還有其他細節，但總的來說，使用標準CMOS技術可以達到幾乎任何TID硬度水平，但是SOI有一些基本限制。 這些限制對於低軌道空間應用通常可以忽略不計，但是如果我們談論的是核工業中可能存在的多梅加拉德水平，那麼SOI必須進行商業上不可行的技術變革。

Single event upsets in SOI are no less interesting. On the one hand, the charge collection volume in SOI is much smaller (although there is a long-lasting argument about the exact shape of this volume and its possible connection to the bulk). This means that we get less excessive charge and can dissipate it through supply lines faster, increasing chances of logic masking in cases on non-memory cells being hit.

SOI中的單事件失敗也同樣有趣。 一方面，SOI中的電荷收集體積要小得多(儘管對此體積的確切形狀及其與主體的可能連接存在長期爭論)。 這意味著我們得到的過量電荷更少，並且可以更快地通過電源線進行耗散，從而在非內存單元被擊中的情況下增加了邏輯屏蔽的機會。

On the other hand, this small area has small capacitance, so even a small deposited charge can raise the voltage and open a parasitic bipolar transistor consisting of source, body and drain. If it happens, the deposited charge is multiplied by the gain of this parasitic transistor. In practice, this means threshold LET drop to levels below 1 MeV * cm ^ 2/(mg), and then effectively any incoming particle will cause a bit upset. 

另一方面，這個小區域的電容很小，因此即使很小的沉積電荷也可以提高電壓並打開由源極，基極和漏極組成的寄生雙極電晶體。 如果發生這種情況，則所沉積的電荷將乘以該寄生電晶體的增益。 實際上，這意味著閾值LET降至低於1 MeV * cm ^ 2 /(mg)的水平，然後有效地，任何進入的粒子都會引起一點不安。

This negative effect, of course, could be mitigated by the careful low-ohmic connection between the transistor body and a respective power bus (or, in some cases, transistor source). But no one does this in commercial chips as these connections take a lot of areas and do nothing in exchange. Even in a radhard chip losing some area in each transistor can be a significant downside compared to bulk alternatives where one contact per 4-8 memory cells is often sufficient to prevent both latchup and parasitic bipolar multiplication. Even some guard rings can be set up with smaller area loss.

當然，可以通過在電晶體主體與相應的電源總線(或在某些情況下為電晶體源)之間進行仔細的低歐姆連接來減輕這種負面影響。 但是沒有人會在商業晶片中做到這一點，因為這些連接佔據了很多領域，卻無所作為。 與批量替代方案相比，即使在radhard晶片中，每個電晶體中損失一些面積也可能是一個重大的缺點，在批量替代方案中，每4-8個存儲單元一個觸點通常足以防止閂鎖和寄生雙極乘法。 甚至可以設置一些面積較小的保護環。

SOI gets another important advantage at small process nodes where dielectric isolation helps prevent multiple bit upsets from a single particle, but modern cells are so small that a single ion track can directly affect two of them. However, it’s still much better than 10-bit upsets seen in experiments with bulk technology.

SOI在小型Craft.io節點上獲得了另一個重要的優勢，在這些Craft.io中，電介質隔離有助於防止單個粒子發生多次位翻轉，但是現代單元是如此之小，以至於單個離子軌跡可以直接影響其中兩個。 但是，它仍然比批量技術實驗中看到的10位翻轉要好得多。

Summing things up, SOI is not 「inherently radiation hardened」, but it has some significant advantages and disadvantages compared to traditional bulk technology. The advantages could be exploited for a great effect, while disadvantages should be mitigated with a proper design. But the same is also true for bulk technology, so the proper process choice is not as trivial as it may seem and should be taken seriously in every single project. One should deeply understand the application to achieve desired levels of radiation hardness without making the chip unnecessarily complicated and too expensive.

總結一下，SOI並不是「固有地輻射硬化」的，但是與傳統的批量技術相比，它具有一些明顯的優缺點。 可以充分利用這些優點，而通過適當的設計來減輕這些缺點。 但是對於批量技術來說也是如此，因此正確的過程選擇並不像看起來那樣瑣碎，應該在每個項目中認真對待。 人們應該深刻理解該應用，以達到所需的輻射硬度水平，而不會使晶片變得不必要的複雜和昂貴。

就是這樣，夥計們！ (That's all, folks!)

Many engineers across the globe are working on the topic of radiation hardness, and it’s completely impossible to cover everything in one article, especially if it’s dedicated to a wider audience. So, my colleagues will probably find enough oversimplifications or even mistakes, which I will be happy to discuss and correct. While not trying to be exhaustive, I hope that I gave my readers a brief understanding of what radiation hardening of electronic circuits is and that I was able to dispel some related misconceptions. Microelectronics in general and its special applications are one of the fastest evolving fields of applied science, so common knowledge becomes outdated very fast, while simple recipes are not used just because they don’t exist anymore.

全球許多工程師都在研究輻射硬度這一主題，並且完全不可能在一篇文章中涵蓋所有內容，尤其是當它面向更廣泛的受眾時。 因此，我的同事們可能會發現足夠的過度簡化甚至錯誤，我將很樂於討論和糾正。 儘管我不想窮盡所有，但我希望我能使讀者對電子電路的輻射硬化有一個簡要的了解，並希望我能夠消除一些相關的誤解。 總體而言，微電子學及其特殊應用是應用科學領域發展最快的領域之一，因此，常識變得非常過時，而不再使用簡單的食譜，因為它們不再存在。

翻譯自: https://habr.com/en/post/518366/

數字集成電路面試常見問題